The present disclosure relates to an analog to digital (AD) converter and a signal processing system for converting an analog signal into a digital signal.
An AD converter of the pipeline type is used popularly as an AD converter having a sampling frequency around 100 MS/s and having a resolution of 8 to 14 bits.
This is because a pipeline type AD converter exhibits the following merits in comparison with a parallel type AD converter wherein processing of N bits is carried out at a time by two to n-th power comparators in one clock cycle.
In particular, an AD converter of the pipeline type has such merits that the number of comparators is small, that a comparator of high accuracy is not required and that processing of N bits may be carried out divisionally in several clock cycles. Therefore, a pipeline type AD converter is used widely in comparison with a parallel type AD converter.
Here, operation of a pipeline type AD converter is described taking a case in which a 10-bit AD converter is implemented using an MDAC which carries out 1-bit processing per one stage as an example. An input signal is represented by Vin, and a reference voltage is represented by Vr. It is assumed that the input signal and the reference voltage satisfy 0<Vin<Vr.
First, in a first clock cycle, the MDAC of the first stage samples the input signal Vin, and which one of Vin<Vr/2 and Vin>Vr/2 is satisfied is decided by a comparator.
In the case of Vin>Vr/2, subtraction is carried out by the MDAC of the first stage to produce a signal of Vin−Vr/2, and this signal is doubled by an amplifier to produce and output an analog residual signal 2Vin−Vr. Concurrently, a digital signal 1 (MSB) is outputted.
In a next clock cycle, the MDAC of the second stage samples the analog residual signal output 2Vin−Vr of the MDAC of the first stage, and the sampled value is compared with Vr/2 by another comparator. At this time, the MDAC of the first stage samples a next analog input signal and repeats the processing carried out within the first clock cycle.
If 2Vin−Vr>Vr/2 is obtained by the MDAC of the second stage, then a subtraction process of (2Vin−Vr)−Vr/2 is carried out, and then a resulting value is doubled by an amplifier to produce and output an analog residual signal 4Vin−3Vr. Concurrently, a digital signal 1 is outputted.
Similar operation is repeated by the MDACs connected in series to produce and output a digital signal of 10 bits in 10 clock cycles.